TIMING & CONTROL UNIT

CONTROL SIGNAL

DESCRIBE DIFFERENT TIMING & CONTROL SIGNALS

Clock

To enable the µp a CLOCK pulse is used . Some of µp have o chip internal clock generator whose frequency is controlled by an external crystal only while some require external clock input . 8-bit µp normally uses a clock of clock of frequency ranging from 3 MHZ to 10 MHZ .

RESET

Reset input normally forces all the control registers to a predetermined state . The PC is reset to zero in many processor so that the µp starts executing the program stored in memory location zero . In some µp , the reset address could be different from zero .

INTERRUPT

When an interrupt input is activated, the CPU stops executing the current program , the PC is stored in the stack and loaded with address of the interrupt. The CPU starts executing the interrupt instructions . There are two types of interrupt , Maskable & Non-Maskable interrupt . The Maskable interrupt can be disabled by software and Non-Maskable interrupt can be disabled by external hardware . There are more than one interrupts in a microprocessor . The CPU has on-chip timers(USART) which process interrupt facility and they are internally requested interrupt . After the interrupt instruction is executed it produces a RETURN instruction which is executed during the interrupt service routine , the PC is loaded by the the contents of the STACK and CPU starts executing the main program .

HOLD

During the HOLD state the peripheral devices are allowed to take the control of the data and address bus for transferring data to or from memory . When a microprocessor gets a HOLD input , it stops the execution and remains in no operation(nop) mode and the address and data bus becomes floating . So at this time the I/O ports has direct memory access .

HOLD ACKNOWLEDGE

When microprocessor accepts the HOLD instruction on the request of I/P ports or external peripheral devices for direct memory access , the CPU goes into HOLD state and it sends a signal to the I/P peripherals as HLDA output so that the I/P port or external devices can understand that the CPU accepts the HOLD request and the two bus is free to use . This type of communication is called Handshsking .

READ & WRITE

These control signals are used to communicate with the I/P ports and the memory . When a data is required to be fetched from the memory or an input port , the respective port or memory is first enabled , then READ output becomes active and the port or the memory gives data to the data bus . Similarly when a data is required to store in memory or output port , the respective port or memory is first enabled and then WRITE output becomes active and the memory stores the data .

IOR & MR

When the CPU requires to communicate with an I/P port , the IOR output becomes active and when CPU addresses a memory location , MR output becomes active . These outputs along with the higher bits of the address bus are used to select any particular memory device , I/P port or external device for communication with CPU .

ALE

The address latch enable control signal is a special output . Microprocessor have 8-bit data bus multiplexed with lower half of 16-bit address bus . This signal is used to demultiplex the address bus from the common address data and address bus with the help of an external latching device . Before each of the fetching or RD/WR operations , this output becomes active .

RESET IN

When the signal on this pin goes low , the counter is set to 0 , the buses are tri-stated , and the MPU is reset .

RESET OUT

This signal indicates that the MPU is being reset and it is active high . This signal can be used to reset other devices .

READY

This signal is used to delay the microprocessor READ or WRITE cycles until a slow responding peripheral is ready to send or accept data . When this signal goes low , the microprocessor waits for a predefined integral number of clock cycle until it goes high .